1. Field of the Invention
This invention generally relates to binary non-return to zero (NRZ) communications and, more particularly, to a system and method for acquiring voltage controlled oscillator (VCO) frequency ranges, generating a reference clock, and for generating a recovered clock in the absence of a data stream.
2. Description of the Related Art
Voltage controlled ring oscillators are commonly used in monolithic clock data recovery (CDR) units, as they're easy to fabricate provide reliable results. Ring oscillators obtain their tuning characteristics by changing the variable delay around the ring, usually in response to a dedicated control voltage input (tuning voltage). Voltage controlled ring oscillators can, and usually do exhibit a tuning range much wider than the closed loop PLL bandwidth of the circuits in which they operate.
Clock recovery phase-locked loops (PLLs) generally don't use phase-frequency detectors (PFDs) in the data path since the incoming data signal isn't deterministic. PFDs are more typically used in frequency synthesizers with periodic (deterministic) signals. Clock recovery PLLs use exclusive-OR (XOR) based phase detectors to maintain quadrature phase alignment between the incoming data pattern and the re-timed pattern. XOR based phase detectors have limited frequency discrimination capability, generally restricting frequency offsets to less than the closed loop PLL bandwidth. This characteristic, coupled with the wide tuning range of the VCO, requires CDR circuits to depend upon an auxiliary frequency acquisition system.
There are two basic PLL frequency acquisition techniques. The first is a VCO sweep method. During an out-of-lock condition, auxiliary circuits cause the VCO frequency to slowly sweep across its tuning range in search of an input signal. The sweeping action is halted when a zero-beat note is detected, causing the PLL to lock to the input signal. The VCO sweep method is generally used in microwave frequency synthesis applications. The second type of acquisition aid, commonly found in clock recovery circuits, uses a PFD in combination with an XOR phase detector. When the PLL isn't locked to a data stream, the PLL switches over to a PFD that is driven by a stable reference clock source. The reference clock frequency is approximately equal to the data stream rate. Thus, the VCO frequency is held very close to the data rate. Keeping the VCO frequency in the proper range of operation facilitates acquisition of the serial data and maintains a stable downstream clock when serial data isn't present at the CDR input. When serial data is applied to the CDR, the XOR based phase detector replaces the PFD, and data re-timing resumes.
It would be advantageous if a CDR or a clock synthesis unit (CSU) had the ability to operate over a broad range of clock frequencies.
It would be advantageous if the CDR/CSU units could simultaneously maintain clock stability when the data stream to the receiver input is lost.
It would also be advantageous if the CDR/CSU units had an automatic data stream rate detection system.